Integrated circuits (ICs) are generally susceptible to damage from electrostatic discharge (ESD) events. An ESD event typically occurs when an IC is handled by human beings or by machines. During the ESD event, a large voltage is applied across pads of the IC. To avoid damage to the IC during an ESD event, ESD protection devices are typically fabricated on the IC and connected to the pads of the IC. The ESD protection devices provide discharge paths so that the internal circuits of the IC are not damaged during the ESD event.
FIG. 1 is a schematic diagram of a typical prior art ESD protection circuit 101. Input pad 102 is connected to input buffer 103, which in turn is connected to other elements of the integrated circuit. ESD protection circuit 101 includes a p-channel pull-up transistor 104 and an n-channel pull-down transistor 105. Pull-up transistor 104 has a drain and gate coupled to the V.sub.CC voltage supply rail and a source coupled to input pad 102. Pull-down transistor 105 has a drain coupled to input pad 102 and a source and gate coupled to the ground supply rail.
ESD events can result in the application of either a positive or negative voltage pulse to pad 102. This voltage pulse is connected either across pad 102 and the V.sub.CC supply rail or across pad 102 and the ground supply rail. A positive ESD pulse applied across pad 102 and the ground supply rail will tend to induce n-junction breakdown in grounded gate n-channel ESD transistor 105, while a negative ESD pulse applied across pad 102 and the ground supply rail will cause the n-junction which exists between the drain and the substrate of transistor 105 to turn on, thereby enabling transistor 105 to conduct current as a parasitic bipolar transistor. Conversely, a positive ESD pulse applied across pad 102 and the V.sub.CC supply rail will turn on the p-junction of which exists between the source and the substrate of transistor 104, while a negative ESD pulse applied across pad 102 and the ground supply rail will tend to induce p-junction breakdown in p-channel ESD transistor 104.
In general, ESD protection circuit 101 provides better ESD protection when an ESD transistor is operating in turn-on mode, rather than breakdown mode. This is because operating an ESD transistor in breakdown mode results in a non-uniform current distribution which is very sensitive to any defect or process variation affecting breakdown voltage. As a result of this non-uniform current distribution, ESD transistors can be locally destroyed when operated in breakdown mode. In contrast, when ESD transistor is operated in turn-on mode, the ESD transistor has a uniform current distribution which is insensitive to defects or process variations.
Moreover, the breakdown voltage of an ESD transistor is generally more than 10 volts, while the turn-on voltage of the same transistor is typically less than 5 volts. The higher voltage experienced when operating in breakdown mode results in a greater heating effect within the ESD transistor, when compared with the heating effect experienced when operating in turn-on mode (for a given amount of ESD charge).
While circuit 101 allows transistors 104 and 105 to operate in turn-on mode for certain ESD events, the maximum positive voltage which can be applied to pad 102 during normal operation is limited to approximately Vcc plus 0.5 volts. If the applied voltage exceeds this level, transistor 104 turns on and current flows from pad 102 to the V.sub.CC supply rail of the IC through p-channel transistor 104. Normally, this is not allowed in IC operation specifications. The limitation of a maximum pad voltage is particularly undesirable in ICs having a V.sub.CC supply voltage of 3.3 volts or lower. Generally, IC users would like to have a 3.3 volt IC which can receive a 5.5 volt voltage when interfacing with an IC having a V.sub.CC supply voltage of 5 volts.
It would therefore be desirable to have an ESD structure which turns on for both positive and negative ESD pulses and which turns on at voltage levels which are low enough to prevent excessive heating and high enough to prevent the pad from shorting to the supply rails during normal operating conditions.